In electronic device testing, a pin driver on a test system may provide a voltage pulse stimulus to a device under test (DUT) at a specific time and may measure a response from the DUT, to determine whether the DUT meets a range of parameters of its device specification. The quality of a test system may be determined by the waveform fidelity (ideality) and timing precision of the voltage pulse it provides. Spurious signals (switching transients) in the voltage pulses may be produced during voltage level transitions, and may impact both fidelity and timing accuracy.
An ideal voltage level transition may be defined as a linear voltage transition between two voltage levels. An actual voltage level transitioning may include deviations, such as overshoots, undershoots, pre-shoots, and slew nonlinearity, caused by spurious signals. These deviations negatively impact timing precision and need be minimized.
Spurious signals may be caused by parasitic capacitance in the voltage driver circuits of the test system. Dominant parasitic capacitance sources may include metal interconnect routing and device junction capacitances, which are both related to the physical switch/transistor size in the voltage driver circuits.
In order to test a variety of electronic devices, an automatic test system may need to drive a pin with voltage level transitions between different voltage extremes using different techniques. For example, memory devices may typically be tested using ‘class A’ techniques, which may require limited voltage swing ranges (swing of 25 mV to 500 mV for example) that also limits device power consumption in the memory devices. Other devices may be tested using ‘class AB’ techniques, which may require higher voltage transition speed and greater voltage swing ranges (>500 mV or >5V for example).
Some devices may have pins that need to be tested using both limited voltage swing ranges and greater voltage swing ranges, may thus require the test system, for example, to test the pins using both ‘class A’ techniques and ‘class AB’ techniques. This additional capability requirement poses a problem in test system design, that the test system need to be capable of driving large voltage swing ranges fast enough and driving small voltage swing ranges with high fidelity and few spurious signals.
Switch sizes of test systems may be designed based on the slew current requirements needed to meet the maximum transition speed requirement. In other words, in order to drive a pin with a relatively large voltage swing range in a small amount of time, the driver circuit may need to be able to produce relatively large amount of slew current, by having large switch size in the driver circuit.
Large switch size may correspond to large parasitic capacitance. The resultant spurious signals may be small, relative to the overall large voltage swing range. However, if the same driver circuit with large switch size is used to drive smaller voltage swing ranges, the same spurious signals may become relatively larger in proportion, and thus would significantly and negatively impact timing precision.
Thus, there is a need for an improved pin driver that can produce high swing fidelity when driving a variety of different voltage swing ranges.